The Cache Memory Simulation Program was designed taken into consideration the results of the evaluation of existing web-based simulation programs as well as the students' learning difficulties. The program aims at helping students to have a better understanding of the cache memory operation.
Educational material about cache memory is available in:
(www.di.uoa.gr/architecture) Computer Architecture, Chapter 4 (only in greek)
(hermes.di.uoa.gr/inspire) Adaptive educational system.
The design principles are:
- The design and the implementation of a cache memory simulation program that uses real data. For that reason, we set the main memory size equal to 1MB, the cache memory size equal to 8KB and the size of cache memory block equal to 16B or 32B.
- The visualization of the internal structure of the C.P.U. (e.g. registers), the cache memory (e.g. blocks, sets, identification circuits) and the main memory (e.g. address, data), the communication buses between units, and, in details, the animation of the operations' steps.
- The detailed visualization, by using multiple representations, of operation' steps: identification (e.g. address bit partitioning, circuits), placement (e.g. updating of the cache block's tag field and valid bit) and replacement.
- The students' option to select:
- the command (read / write) that will be executed by the C.P.U,
- the block size,
- the cache organization,
- the replacement policy,
- the write policy and
- a specific main memory address.
In more details students can select:
- The block size of the cache memory
- The organization type of the cache memory of 8 KB size
- The replacement policy
- The write policy in case of hit
- The write policy in case of miss
Also students can select:
- the command (read / write) that will be executed by the C.P.U
- Main memory address. The user can select the desired main memory address either by moving the scroll bar or by using the arrow keys, or the Page up/Page down keys.
Return to Main Menu.